Bit masking valid sectors for write-back coalescing

ABSTRACT

A processing device identifies a portion of data in a cache memory to be written to a managed unit of a separate memory device and determines, based on respective memory addresses, whether an additional portion of data associated with the managed unit is stored in the cache memory. The processing device further generates a bit mask identifying a first location and a second location in the managed unit, wherein the first location is associated with the portion of data and the second location is associated with the additional portion of data, and performs, based on the bit mask, a read-modify-write operation to write the portion of data to the first location in the managed unit of the separate memory device and the additional portion of data to the second location in the managed unit of the separate memory device.

RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.16/697,510, filed Nov. 27, 2019, which is hereby incorporated in itsentirety herein by reference.

TECHNICAL FIELD

Embodiments of the disclosure relate generally to memory sub-systems,and more specifically, relate to bit masking valid sectors forwrite-back coalescing.

BACKGROUND

A memory sub-system can include one or more memory components that storedata. The memory components can be, for example, non-volatile memorycomponents and volatile memory components. In general, a host system canutilize a memory sub-system to store data at the memory components andto retrieve data from the memory components.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detaileddescription given below and from the accompanying drawings of variousembodiments of the disclosure.

FIG. 1 illustrates an example computing environment that includes amemory sub-system, in accordance with some embodiments of the presentdisclosure.

FIG. 2 is a flow diagram of an example method to generate a bit mask forwrite-back coalescing, in accordance with some embodiments of thepresent disclosure.

FIG. 3 is a flow diagram of an example method to perform a writeoperation using a bit mask for write-back coalescing, in accordance withsome embodiments of the present disclosure.

FIG. 4 illustrates a memory sub-system using a bit mask for write-backcoalescing in accordance with some embodiments of the presentdisclosure.

FIG. 5 is illustrates generation of data bit mask based on codewordsstored in cache media in accordance with some embodiments of the presentdisclosure.

FIGS. 6A and 6B illustrate using a bit mask to write multiple codewordsto a managed unit in a single write operation in accordance with someembodiments of the present disclosure.

FIG. 7 is a block diagram of an example computer system in whichembodiments of the present disclosure may operate.

DETAILED DESCRIPTION

Aspects of the present disclosure are directed to bit masking validsectors for cache write-back coalescing. A memory sub-system can be astorage device, a memory module, or a hybrid of a storage device andmemory module. Examples of storage devices and memory modules aredescribed below in conjunction with FIG. 1. In general, a host systemcan utilize a memory sub-system that includes one or more memory devicesthat store data. The host system can provide data to be stored at thememory sub-system and can request data to be retrieved from the memorysub-system.

A memory module can include a memory component, such asthree-dimensional cross-point (3DXP) memory. The memory component canhave a large data access granularity compared to the access granularityof another memory component, such as a cache media. Data accessgranularity can be the size of data that can be retrieved from a memorycomponent in a single operation. The larger the data access granularity,the larger the amount of data that can be retrieved from a memorycomponent in a single operation. Due to the disparity between the accessgranularity of the cache media and the memory component, write-backsfrom the cache media to the memory component can require additionaloperations, such as a read-modify-write operation. A write-back can be awrite of new or updated data from a cache at which the data is modified(based on writes received from a host system) to a memory componentwhere the data is stored. The read-modify-write operation can includereading an entire managed unit from the memory component, modifying thedata (i.e., the modify portion of a read-modify-write operation) of themanaged unit according to the write from the cache media and writing themodified data of managed unit back to the memory component. A managedunit can be a set of smaller portions of data, referred to as codewords,which are grouped together for media management and data accesspurposes. In some instances, the cache media can include multipleportions of data, or cache lines, associated with codewords of themanaged unit.

The codewords of the managed unit can be modified (i.e., written to)while in the cache media as cache lines and then written back to themanaged unit. When a codeword is written to in the managed unit, aredundant array of independent disks (RAID) parity bit codeword can alsobe modified based on the new data written to the codeword. The RAIDcodeword can be used for data protection of the codewords included inthe managed unit. The RAID parity codeword can be updated according tothe modified codeword. In conventional memory modules, the multiplecache lines in the cache media can require multiple read-modify-writeoperations to write all the codewords from the cache lines back to themanaged unit. Updating the RAID parity codeword can also includeadditional operations to update according to each modified codewordindividually. The multiple writes and RAID bit updates for theadditional codewords can increase latency and reduce system performance.The additional writes and RAID update operations can also increase mediawear.

Aspects of the present disclosure address the above and otherdeficiencies by providing the ability to coalesce writes to a commonmanaged unit using a bit mask. A cache controller can manage the cachemedia and determine the data to be stored or removed from the cachemedia. If the cache controller determines that a cache linecorresponding to a codeword in the MU is to be written back to the MU,the cache controller can also determine whether additional cache linescorrespond to a codeword of the MU. If there are any additional cachelines corresponding to the MU to be written back to the media, the cachecontroller can generate a bit mask identifying the codeword locations ofthe cache lines to be written back to the MU. The cache lines can thenbe written to the MU in a single write operation using the bit mask. Forexample, a media manager can receive each of the cache lines and the bitmask from the cache controller and interpret the bit mask to identifythe codeword locations in the MU to write each cache line to. The mediamanager can read the MU, modify the MU by applying the mask andinserting the cache lines to the corresponding codeword locations, andthen write the modified MU back to the media. The media manager canupdate the RAID codeword by reading the RAID codeword and performing alogic operation according to each of the modified codeword prior towriting it back to the managed unit.

Therefore, the ability to coalesce write-back operations using a bitmask could increase the lifetime of memory sub-systems due to reductionin read-modify-write operations and reading and writing of RAID paritybits at the media. The write latency of the memory sub-system could bereduced because the cache media is managed more efficiently bywriting-back all sectors or codewords in the cache media that belong toa common managed unit in a single write operation. Finally, the writelatency could be reduced due to reduction in the number of read andwrites of the RAID codeword.

FIG. 1 illustrates an example computing system 100 that includes amemory sub-system 110 in accordance with some embodiments of the presentdisclosure. The memory sub-system 110 can include media, such as one ormore volatile memory devices (e.g., memory device 140), one or morenon-volatile memory devices (e.g., memory device 130), or a combinationof such.

A memory sub-system 110 can be a storage device, a memory module, or ahybrid of a storage device and memory module. Examples of a storagedevice include a solid-state drive (SSD), a flash drive, a universalserial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC)drive, a Universal Flash Storage (UFS) drive, and a hard disk drive(HDD). Examples of memory modules include a dual in-line memory module(DIMM), a small outline DIMM (SO-DIMM), and a non-volatile dual in-linememory module (NVDIMM).

The computing system 100 can be a computing device such as a desktopcomputer, laptop computer, network server, mobile device, a vehicle(e.g., airplane, drone, train, automobile, or other conveyance),Internet of Things (IoT) enabled device, embedded computer (e.g., oneincluded in a vehicle, industrial equipment, or a networked commercialdevice), or such computing device that includes memory and a processingdevice.

The computing system 100 can include a host system 120 that is coupledto one or more memory sub-systems 110. In some embodiments, the hostsystem 120 is coupled to different types of memory sub-system 110. FIG.1 illustrates one example of a host system 120 coupled to one memorysub-system 110. As used herein, “coupled to” generally refers to aconnection between components, which can be an indirect communicativeconnection or direct communicative connection (e.g., without interveningcomponents), whether wired or wireless, including connections such aselectrical, optical, magnetic, etc.

The host system 120 can include a processor chipset and a software stackexecuted by the processor chipset. The processor chipset can include oneor more cores, one or more caches, a memory controller (e.g., NVDIMMcontroller), and a storage protocol controller (e.g., PCIe controller,SATA controller). The host system 120 uses the memory sub-system 110,for example, to write data to the memory sub-system 110 and read datafrom the memory sub-system 110.

The host system 120 can be coupled to the memory sub-system 110 via aphysical host interface. Examples of a physical host interface include,but are not limited to, a serial advanced technology attachment (SATA)interface, a peripheral component interconnect express (PCIe) interface,universal serial bus (USB) interface, Fibre Channel, Serial AttachedSCSI (SAS), a dual in-line memory module (DIMM) interface (e.g., DIMMsocket interface that supports Double Data Rate (DDR)), etc. Thephysical host interface can be used to transmit data between the hostsystem 120 and the memory sub-system 110. The host system 120 canfurther utilize an NVM Express (NVMe) interface to access the memorycomponents (e.g., memory devices 130) when the memory sub-system 110 iscoupled with the host system 120 by the PCIe interface. The physicalhost interface can provide an interface for passing control, address,data, and other signals between the memory sub-system 110 and the hostsystem 120.

The memory devices can include any combination of the different types ofnon-volatile memory devices and/or volatile memory devices. The volatilememory devices (e.g., memory device 140) can be, but are not limited to,random access memory (RAM), such as dynamic random access memory (DRAM)and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device 130)include negative-and (NAND) type flash memory and write-in-place memory,such as three-dimensional cross-point (“3D cross-point”) memory. Across-point array of non-volatile memory can perform bit storage basedon a change of bulk resistance, in conjunction with a stackablecross-gridded data access array. Additionally, in contrast to manyflash-based memories, cross-point non-volatile memory can perform awrite in-place operation, where a non-volatile memory cell can beprogrammed without the non-volatile memory cell being previously erased.

Each of the memory devices 130 can include one or more arrays of memorycells. One type of memory cell, for example, single level cells (SLC)can store one bit per cell. Other types of memory cells, such asmulti-level cells (MLCs), triple level cells (TLCs), and quad-levelcells (QLCs), can store multiple bits per cell. In some embodiments,each of the memory devices 130 can include one or more arrays of memorycells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. Insome embodiments, a particular memory device can include an SLC portion,and an MLC portion, a TLC portion, or a QLC portion of memory cells. Thememory cells of the memory devices 130 can be grouped as pages that canrefer to a logical unit of the memory device used to store data. Withsome types of memory (e.g., NAND), pages can be grouped to form blocks.Some types of memory, such as 3D cross-point, can group pages acrossdice and channels to form management units (MUs).

Although non-volatile memory components such as 3D cross-point type andNAND type flash memory are described, the memory device 130 can be basedon any other type of non-volatile memory, such as read-only memory(ROM), phase change memory (PCM), self-selecting memory, otherchalcogenide based memories, ferroelectric random access memory (FeRAM),magneto random access memory (MRAM), negative-or (NOR) flash memory,electrically erasable programmable read-only memory (EEPROM).

A memory sub-system controller 115 (or controller 115 for simplicity)can communicate with the memory devices 130 to perform operations suchas reading data, writing data, or erasing data at the memory devices 130and other such operations. The memory sub-system controller 115 caninclude hardware such as one or more integrated circuits and/or discretecomponents, a buffer memory, or a combination thereof. The hardware caninclude a digital circuitry with dedicated (i.e., hard-coded) logic toperform the operations described herein. The memory sub-systemcontroller 115 can be a microcontroller, special purpose logic circuitry(e.g., a field programmable gate array (FPGA), an application specificintegrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller 115 can include a processor (processingdevice) 117 configured to execute instructions stored in local memory119. In the illustrated example, the local memory 119 of the memorysub-system controller 115 includes an embedded memory configured tostore instructions for performing various processes, operations, logicflows, and routines that control operation of the memory sub-system 110,including handling communications between the memory sub-system 110 andthe host system 120.

In some embodiments, the local memory 119 can include memory registersstoring memory pointers, fetched data, etc. The local memory 119 canalso include read-only memory (ROM) for storing micro-code. While theexample memory sub-system 110 in FIG. 1 has been illustrated asincluding the memory sub-system controller 115, in another embodiment ofthe present disclosure, a memory sub-system 110 may not include a memorysub-system controller 115, and may instead rely upon external control(e.g., provided by an external host, or by a processor or controllerseparate from the memory sub-system).

In general, the memory sub-system controller 115 can receive commands oroperations from the host system 120 and can convert the commands oroperations into instructions or appropriate commands to achieve thedesired access to the memory devices 130. The memory sub-systemcontroller 115 can be responsible for other operations such as wearleveling operations, garbage collection operations, error detection anderror-correcting code (ECC) operations, encryption operations, cachingoperations, and address translations between a logical address (e.g.,logical block address (LBA), namespace) and a physical address (e.g.,physical MU address, physical block address) that are associated withthe memory devices 130. The memory sub-system controller 115 can furtherinclude host interface circuitry to communicate with the host system 120via the physical host interface. The host interface circuitry canconvert the commands received from the host system into commandinstructions to access the memory devices 130 as well as convertresponses associated with the memory devices 130 into information forthe host system 120.

The memory sub-system 110 can also include additional circuitry orcomponents that are not illustrated. In some embodiments, the memorysub-system 110 can include a cache or buffer (e.g., DRAM) and addresscircuitry (e.g., a row decoder and a column decoder) that can receive anaddress from the memory sub-system controller 115 and decode the addressto access the memory devices 130.

In some embodiments, the memory devices 130 include local mediacontrollers 135 that operate in conjunction with memory sub-systemcontroller 115 to execute operations on one or more memory cells of thememory devices 130. An external controller (e.g., memory sub-systemcontroller 115) can externally manage the memory device 130 (e.g.,perform media management operations on the memory device 130). In someembodiments, a memory device 130 is a managed memory device, which is araw memory device combined with a local controller (e.g., localcontroller 135) for media management within the same memory devicepackage. An example of a managed memory device is a managed NAND (MNAND)device.

The memory sub-system 110 includes a write-back coalescing component 113that can be used to coalesce write-backs from cache media to a memorycomponent. In some embodiments, the memory sub-system controller 115includes at least a portion of the write-back coalescing component 113.For example, the memory sub-system controller 115 can include aprocessor 117 (processing device) configured to execute instructionsstored in local memory 119 for performing the operations describedherein. In some embodiments, the write-back coalescing component 113 ispart of the host system 110, an application, or an operating system.

The write-back coalescing component 113 can identify cache lines in acache media corresponding to codewords of a single managed unit of amemory component. The write coalescing component 113 can generate a bitmask for the cache lines corresponding to the codewords of the managedunit in the memory component. The write-back coalescing component 113can write the cache lines to the managed unit in a single write usingthe bit mask to identify codeword locations of the managed unit to writethe cache lines to. Further details with regards to the operations ofthe write-back coalescing component 113 are described below.

FIG. 2 is a flow diagram of an example method 200 to generate a bit maskfor write-back coalescing, in accordance with some embodiments of thepresent disclosure. The method 200 can be performed by processing logicthat can include hardware (e.g., processing device, circuitry, dedicatedlogic, programmable logic, microcode, hardware of a device, integratedcircuit, etc.), software (e.g., instructions run or executed on aprocessing device), or a combination thereof. In some embodiments, themethod 200 is performed by the write-back coalescing component 113 ofFIG. 1. Although shown in a particular sequence or order, unlessotherwise specified, the order of the processes can be modified. Thus,the illustrated embodiments should be understood only as examples, andthe illustrated processes can be performed in a different order, andsome processes can be performed in parallel. Additionally, one or moreprocesses can be omitted in various embodiments. Thus, not all processesare required in every embodiment. Other process flows are possible.

At operation 210, the processing logic of a memory sub-system identifiesa portion of data in a cache memory to be written to a managed unit of amemory component. The portion of data in the cache memory can be a cacheline of data stored in the cache memory. A cache line can be a certainamount of data, such as a sector or codeword of the managed unit. Acache controller can include caching policies, such as evictionpolicies, in which cache lines stored in the cache memory are writtenback to the managed unit of the memory component under certainconditions. For example, a cache line can be evicted from the cachemedia when a new codeword is to be written to the cache media and thecache line is the least recently used cache line. Additionally, when acache line in the cache memory has been modified (i.e., is dirty) thenthat data should be written back to the managed unit to store the dataprior to removing the data from the cache media. In another example, allcache lines stored in the cache media are written back to the memorycomponent upon eviction.

The cache line can be associated with a particular location within themanaged unit of the memory component. The particular location within themanaged unit can be referred to as a sector, or a codeword. A codewordcan contain a particular amount of data (e.g., 64 bytes, 128 bytes,etc.) When a codeword is accessed, by a host system it can be retrievedfrom the managed unit of the memory component and placed in the cachememory from which the host system can access the data quickly. Anymodifications that are made to the data in the cache memory may not beimmediately written to the managed unit of the memory component. Thus,the modifications to the data can be written back to the managed unit onthe media to ensure that the changes to the data persist.

At operation 220, the processing logic determines whether an additionalportion of data in the cache memory associated with the managed unit isstored at the cache memory. The additional portion of data in the cachememory can be another cache line of data stored in the cache memory. Theadditional portion of data in the cache memory can be associated withanother location (i.e., codeword) within the managed unit. The cachecontroller can determine that portion of data and the additional portionof data are associated with the same managed unit using theircorresponding addresses. The managed unit can have a base address andinclude all data within a defined number of bytes from the base address.For example, the managed unit can contain one kilobyte of data, which issegmented into eight portions of 128 byte codewords. The managed unitcan thus include all addresses from the base address to the base addressplus one kilobyte. Once the cache controller identifies the portion ofdata at operation 210, the cache controller can identify the baseaddress of the managed unit and then determine whether any otherportions of data within the cache memory have addresses within themanaged unit's address range.

At operation 230, the processing logic generates a bit mask identifyingthe locations of the managed unit associated with the portion of dataand the additional portion of data. The bit mask can include a bit foreach codeword located within the managed unit. Thus, each bit canindicate whether the cache memory includes a portion of data associatedwith each particular codeword. For example, each bit that is set as a 1can indicate that cache line is stored in the cache media correspondingto that codeword, and each bit set as a 0 indicates that the cachememory does not include data for the corresponding codeword, or viceversa.

At operation 240, the processing logic performs, based on the bit mask,a write operation to write the portion of data and the additionalportion of data to the managed unit. The write coalescing component caninterpret the bit mask, the portion of data, and the additional portionof data to write the portion of data to its corresponding codeword ofthe managed unit and the additional portion of data to its correspondingcodeword in a single write operation. To perform the write operation,the write coalescing component can perform a read-modify-write operationto the managed unit with both the portion of data and the additionalportion of data. However, if the entire MU is present in the cachememory, then the processing logic can perform a write of the full MUrather than a read-modify-write. The processing logic can read theentire managed unit and then modify a first and second codeword with theportion of data and the additional portion of data according to the bitmask. The bit mask can identify the first codeword to modify with theportion of data, and the second codeword to modify with the additionalportion of data. Once the appropriate codewords are modified, theprocessing logic can write the entire modified managed unit back to thememory component. Thus, rather than performing two separateread-modify-write operations to write the portion of data and theadditional portion of data to the managed unit, the processing logiccoalesces the writes into a single read-modify-write operation. This canbe done for any number of cache lines in the managed unit. For example,any number of codewords, up to the number of codewords in a managedunit, can be coalesced in the single write operation. Additionally, ifall codewords of the managed unit are stored in the cache memory then awrite operation of the entire managed unit can be performed rather thana read-modify-write.

In addition, the processing logic can additionally update a RAID paritycodeword of the managed unit when the write operation is performed. Toupdate the RAID parity bits of the managed unit, the processing logiccan perform a logic operation on the RAID parity bits and each of themodified codewords. For example, the processing logic can perform an XORoperation of the first codeword and the RAID parity bits and another XORoperation on the second codeword and the RAID parity bits resulting fromthe previous XOR operation. The processing logic can then write theupdated RAID parity bits back to the managed unit.

FIG. 3 is a flow diagram of an example method 300 to perform a writeoperation using a bit mask for write-back coalescing, in accordance withsome embodiments of the present disclosure. The method 300 can beperformed by processing logic that can include hardware (e.g.,processing device, circuitry, dedicated logic, programmable logic,microcode, hardware of a device, integrated circuit, etc.), software(e.g., instructions run or executed on a processing device), or acombination thereof. In some embodiments, the method 300 is performed bythe write-back coalescing component 113 of FIG. 1. Although shown in aparticular sequence or order, unless otherwise specified, the order ofthe processes can be modified. Thus, the illustrated embodiments shouldbe understood only as examples, and the illustrated processes can beperformed in a different order, and some processes can be performed inparallel. Additionally, one or more processes can be omitted in variousembodiments. Thus, not all processes are required in every embodiment.Other process flows are possible.

At operation 310, processing logic of a memory sub-system receives afirst portion of data from a cache media component that is to be writtento a managed unit of a memory component. The first portion of data canbe a cache line stored in the cache media component. The first portionof data can correspond to a sub-set of data stored at the managed unit(i.e., a codeword) of the memory component. The managed unit can be alarger collection of codewords that are grouped together for memorymanagement and data access. In some embodiments, the managed unitcorresponds to the access granularity of the memory component. The firstportion of data can thus be a cache line that is associated with aparticular codeword of the managed unit. The first portion of memory canbe smaller than the access granularity of the managed unit and thereforeto write the portion of data, the processing logic can perform aread-modify-write operation on the managed unit. The processing logiccan read the data of the entire managed unit, modify one or morecodewords of the managed unit and then write the modified data back tothe managed unit.

At operation 320, the processing logic receives a second portion of datain the cache media component that is to be written to the managed unitof the memory component. The second portion of data can be data that isassociated with a second codeword of the managed unit. Thus, both thefirst and second portions of data (or cache lines) are to be written todifferent codewords of the same managed unit. Additionally, any numberof additional portions of data can be identified as to be written to thesame managed unit.

At operation 330, the processing logic receives a bit mask identifyinglocations of the managed unit to which the first portion of data and thesecond portion of data are to be written. The bit mask can be a seriesof bits corresponding to codewords of the managed unit. Each bit of thebit mask can indicate whether new data is to be written to thecorresponding codeword. For example, each bit that is set as a 1 canindicate that cache line is stored in the cache media corresponding tothat codeword, and each bit set as a 0 indicates that the cache memorydoes not include data for the corresponding codeword, or vice versa.Thus, a first bit of the bit mask can indicate that the first portion ofdata is to be written to a first codeword and that the second portion ofdata is to be written to a second codeword. The first and secondcodeword can be non-adjacent, non-contiguous codewords.

At operation 340, the processing logic writes, based on the bit mask,the first and second portion of data from the cache media component tothe managed unit of the memory component in a single write operation. Toperform the write operation, the write coalescing component can performa read-modify-write operation to the managed unit with both the firstportion of data and the second portion of data. The processing logic canread the data from the entire managed unit and modify a first and secondcodeword with the first portion of data and the second portion of data,according to the bit mask. The bit mask can identify the first codewordto modify with the first portion of data, and the second codeword tomodify with the second portion of data. Once the appropriate codewordsare modified, the processing logic can write the entire modified managedunit back to the memory component. Thus, rather than performing multipleread-modify-write operations to write the first portion of data and thesecond portion of data to the managed unit, the processing logiccoalesces the writes into a single read-modify-write operation. Thiscoalescing can be done for any number of cache lines in the managedunit. For example, two, three, four, or more cache lines can becoalesced in a single write operation.

FIG. 4 depicts a memory sub-system 400 using a bit mask for write-backcoalescing. The memory sub-system 400 includes a memory controller 410,a cache media 420, and a memory component 430. The memory controller 410includes a cache controller 412 and a media manager 414, each of whichinclude a write coalescing component 113. The memory controller 410 canmanage storage of data in the memory sub-system 400 and the transfer ofdata between memory components of the memory sub-system 400, such as thecache media 420 and memory component 430. The cache controller 412 caninclude caching polices to manage data from the memory component 430that is cached in the cache media 420. The cache controller 412 candetermine which data to cache, which data to write-back to the memorycomponent 430, and which data to remove from the cache media 420. Mediamanager 414 of the memory controller 410 can manage the data stored atthe memory component 430.

The media manager 414 can access and manage the data in the memorycomponent 430 in one or more groups of data referred to as managed units432A-D. Although depicted as separate components, the cache controller412 and media manager 414 can both be included in a single component ofthe memory controller 410. The media manager 414 can also manage errorcorrection code (ECC) and redundant arrays of independent disk (RAID)parity bits. The ECC and RAID parity bits can provide error correctionand memory protection in case of errors or loss of portions of data. Themedia manager 414 can update the RAID parity bits with each modificationto the data of a managed unit 432A-D. Each managed unit 432A-D can havea RAID parity bit codeword that is read from the managed unit andupdated based on the new data that is written to the managed unit thenwritten back to the managed unit. In one example, the RAID parity bitsare updated by an “exclusive or” (XOR) logic operation between the RAIDparity bits and the new codewords written to the managed unit.

Cache media 420 can be a low latency memory such as DRAM, or SRAM.Portions of data from the memory component 430 can be stored at thecache media 420 (i.e., cache lines 422) so that the data can be accessedquickly by a host system. The cache media 420 can store codewords frommanaged units 432A-D of the memory component 430 as cache lines whichcan be accessed and modified by the host system. The cache media 420 canadditionally store cache line metadata associated with each cache lineindicating a status of the corresponding cache line 422, such as a dirtybit 424 and a valid bit 426. In some embodiments, the cache controller412 can use the dirty bits 424 and valid bits 426 to determine whether acache line has been modified and whether it should be written back tothe memory component 430. For example, as depicted in FIG. 4, “codeword0,” “codeword 2,” and “codeword 7” are each indicated as dirty andvalid. Thus, codewords 0, 2, and 7 contain valid and dirty data and willeach need to be written back to the memory component 430 before beingremoved from the cache media 420 to ensure the modifications persist.

Memory component 430 can be emerging memory, flash memory, 3DXP, DRAM,etc. Memory component 430 can be a type of media that has a largeraccess granularity and higher access latency than the cache media 420.Memory component 430 can include one or more managed units 432A-D, eachincluding multiple codewords, and/or sectors, of data. The media manager414 can write to each codeword of the managed units 432A-D through aread-modify-write operation. Thus, although the media manager accessesthe memory component 430 at a managed unit granularity, each codewordcan be read and written individually through additional operations(read-modify-write), which can increase the latency of the memorycomponent 430.

In one example, as further illustrated by FIGS. 5 and 6A-B, the writecoalescing component 113 can identify a first cache line in the cachemedia 420 that is to be written back to the memory component 430. Thewrite coalescing component 113 then identifies any additional cachelines that can be written back to the same managed unit as the firstcache line. For example, codeword 0, 2, and 7 can each correspond to acodeword of managed unit 432A. The write coalescing component can thengenerate a bit mask identifying the codewords of the managed unit thatthe cache lines 0, 2, and 7 are to be written to. Using the bit mask,the write coalescing component 113 of the media manager 414 can writeeach of the cache lines 0, 2, and 7 to the managed unit 432A in a singlewrite operation. Additionally, the write-back coalescing component 113of the media manager 414 can read and update the RAID parity bits of thea managed unit 432A-D to which the operation occurs in a single logicaloperation before writing the RAID parity bits back to the managed unit432A-D.

FIG. 5 illustrates generation of a bit mask based on codewords stored incache a media (e.g., cache media 420 of FIG. 4). The write coalescingcomponent 113, depicted in FIGS. 1 and 4, can identify each cache line422 that is associated with a single managed unit 432 to generate a bitmask 510. The cache lines 422 can include data from a codeword of themanaged unit 432. Additionally, while in the cache media the codewordscan be modified to be a new codeword that is to replace the previouscodeword of the managed unit 432. For example, a cache line 422 of thecache media 420 can include “new codeword 0” which corresponds tocodeword 0 of the managed unit 432. The cache media 420 can additionalinclude a new codeword 2 and a new codeword 7, corresponding to codeword2 and codeword 7 of the managed unit, respectively. Each new codewordcan be a clean version, a modified version, or a complete replacement ofthe original codeword from the managed unit 432. As depicted, the bitmask 510 can then be generated to identify each of the codewords of themanaged unit 432 that the new codewords correspond to. New codeword 0corresponds to codeword 0 of the managed unit 432, which is located atthe first position in the managed unit 432. Thus, the bit of the bitmask 510 corresponding to the first position can be set to “1,”identifying that new codeword 0 is to be written to the first positionof the managed unit 432, replacing codeword 0. Similarly, new codeword 2corresponds to position 3 of the managed unit. Thus, the bit of the bitmask 510 corresponding to position 3 can be set to a “1.” Finally, newcodeword 7 can correspond to codeword 7 at position 8. Thus, the bit ofthe bit mask 510 corresponding to position 8 can be set to “1.”

FIG. 6A is a diagram illustrating using a bit mask to perform write-backcoalescing. The bit mask 510, generated according to FIG. 5, can be usedby a write coalescing component 113 to write multiple codewords to themanaged unit 432 in a single write operation. The bit mask 510 includesbits corresponding to each codeword of the managed unit 432. Each bit ofthe bit mask 510 can indicate whether a cache line corresponding to thecodeword is stored in the cache media and/or should be written to thecorresponding codeword.

For example, as depicted in FIG. 6A, bits 0, 2, and 7 are set to 1 toindicate that the corresponding codeword is to be written to. From FIG.5, the new codeword 0 is identified based on its address and the bit 0of the bit mask 510 as the new codeword to be written to the location ofcodeword 0. The new codeword 2 is identified based on its address andbit 2 of the bit mask 510 as the new codeword to be written to thelocation of codeword 2. The new codeword 7 is identified based on itsaddress and bit 8 of the bit mask 510 as the new codeword to be writtento the location of codeword 7.

FIG. 6B is a diagram illustrating a resulting managed unit after using abit mask to perform write-back coalescing, as depicted in FIG. 6A. Asdepicted, during the write operation the codewords identified by the bitmask 510 can be replaced by the new codewords from the cache lines ofthe cache media. Although not depicted, the managed unit 432 can includea RAID parity bit codeword. A memory manager can use the RAID paritybits to reproduce codewords that have been corrupted. The memory managercan update the RAID parity bits when new codewords are written to themanaged unit 432.

FIG. 7 illustrates an example machine of a computer system 700 withinwhich a set of instructions, for causing the machine to perform any oneor more of the methodologies discussed herein, can be executed. In someembodiments, the computer system 700 can correspond to a host system(e.g., the host system 120 of FIG. 1) that includes, is coupled to, orutilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1)or can be used to perform the operations of a controller (e.g., toexecute an operating system to perform operations corresponding to thewrite-back coalescing component 113 of FIG. 1). In alternativeembodiments, the machine can be connected (e.g., networked) to othermachines in a LAN, an intranet, an extranet, and/or the Internet. Themachine can operate in the capacity of a server or a client machine inclient-server network environment, as a peer machine in a peer-to-peer(or distributed) network environment, or as a server or a client machinein a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box(STB), a Personal Digital Assistant (PDA), a cellular telephone, a webappliance, a server, a network router, a switch or bridge, or anymachine capable of executing a set of instructions (sequential orotherwise) that specify actions to be taken by that machine. Further,while a single machine is illustrated, the term “machine” shall also betaken to include any collection of machines that individually or jointlyexecute a set (or multiple sets) of instructions to perform any one ormore of the methodologies discussed herein.

The example computer system 700 includes a processing device 702, a mainmemory 704 (e.g., read-only memory (ROM), flash memory, dynamic randomaccess memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM(RDRAM), etc.), a static memory 706 (e.g., flash memory, static randomaccess memory (SRAM), etc.), and a data storage system 718, whichcommunicate with each other via a bus 730.

Processing device 702 represents one or more general-purpose processingdevices such as a microprocessor, a central processing unit, or thelike. More particularly, the processing device can be a complexinstruction set computing (CISC) microprocessor, reduced instruction setcomputing (RISC) microprocessor, very long instruction word (VLIW)microprocessor, or a processor implementing other instruction sets, orprocessors implementing a combination of instruction sets. Processingdevice 702 can also be one or more special-purpose processing devicessuch as an application specific integrated circuit (ASIC), a fieldprogrammable gate array (FPGA), a digital signal processor (DSP),network processor, or the like. The processing device 702 is configuredto execute instructions 726 for performing the operations and stepsdiscussed herein. The computer system 700 can further include a networkinterface device 708 to communicate over the network 720.

The data storage system 718 can include a machine-readable storagemedium 724 (also known as a computer-readable medium) on which is storedone or more sets of instructions 726 or software embodying any one ormore of the methodologies or functions described herein. Theinstructions 726 can also reside, completely or at least partially,within the main memory 704 and/or within the processing device 702during execution thereof by the computer system 700, the main memory 704and the processing device 702 also constituting machine-readable storagemedia. The machine-readable storage medium 724, data storage system 718,and/or main memory 704 can correspond to the memory sub-system 110 ofFIG. 1.

In one embodiment, the instructions 726 include instructions toimplement functionality corresponding to a program pulse controlcomponent (e.g., the program pulse control component 113 of FIG. 1).While the machine-readable storage medium 724 is shown in an exampleembodiment to be a single medium, the term “machine-readable storagemedium” should be taken to include a single medium or multiple mediathat store the one or more sets of instructions. The term“machine-readable storage medium” shall also be taken to include anymedium that is capable of storing or encoding a set of instructions forexecution by the machine and that cause the machine to perform any oneor more of the methodologies of the present disclosure. The term“machine-readable storage medium” shall accordingly be taken to include,but not be limited to, solid-state memories, optical media, and magneticmedia.

Some portions of the preceding detailed descriptions have been presentedin terms of algorithms and symbolic representations of operations ondata bits within a computer memory. These algorithmic descriptions andrepresentations are the ways used by those skilled in the dataprocessing arts to most effectively convey the substance of their workto others skilled in the art. An algorithm is here, and generally,conceived to be a self-consistent sequence of operations leading to adesired result. The operations are those requiring physicalmanipulations of physical quantities. Usually, though not necessarily,these quantities take the form of electrical or magnetic signals capableof being stored, combined, compared, and otherwise manipulated. It hasproven convenient at times, principally for reasons of common usage, torefer to these signals as bits, values, elements, symbols, characters,terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar termsare to be associated with the appropriate physical quantities and aremerely convenient labels applied to these quantities. The presentdisclosure can refer to the action and processes of a computer system,or similar electronic computing device, that manipulates and transformsdata represented as physical (electronic) quantities within the computersystem's registers and memories into other data similarly represented asphysical quantities within the computer system memories or registers orother such information storage systems.

The present disclosure also relates to an apparatus for performing theoperations herein. This apparatus can be specially constructed for theintended purposes, or it can include a general purpose computerselectively activated or reconfigured by a computer program stored inthe computer. Such a computer program can be stored in a computerreadable storage medium, such as, but not limited to, any type of diskincluding floppy disks, optical disks, CD-ROMs, and magnetic-opticaldisks, read-only memories (ROMs), random access memories (RAMs), EPROMs,EEPROMs, magnetic or optical cards, or any type of media suitable forstoring electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently relatedto any particular computer or other apparatus. Various general purposesystems can be used with programs in accordance with the teachingsherein, or it can prove convenient to construct a more specializedapparatus to perform the method. The structure for a variety of thesesystems will appear as set forth in the description below. In addition,the present disclosure is not described with reference to any particularprogramming language. It will be appreciated that a variety ofprogramming languages can be used to implement the teachings of thedisclosure as described herein.

The present disclosure can be provided as a computer program product, orsoftware, that can include a machine-readable medium having storedthereon instructions, which can be used to program a computer system (orother electronic devices) to perform a process according to the presentdisclosure. A machine-readable medium includes any mechanism for storinginformation in a form readable by a machine (e.g., a computer). In someembodiments, a machine-readable (e.g., computer-readable) mediumincludes a machine (e.g., a computer) readable storage medium such as aread only memory (“ROM”), random access memory (“RAM”), magnetic diskstorage media, optical storage media, flash memory components, etc.

In the foregoing specification, embodiments of the disclosure have beendescribed with reference to specific example embodiments thereof. Itwill be evident that various modifications can be made thereto withoutdeparting from the broader spirit and scope of embodiments of thedisclosure as set forth in the following claims. The specification anddrawings are, accordingly, to be regarded in an illustrative senserather than a restrictive sense.

What is claimed is:
 1. A method comprising: identifying a portion ofdata in a cache memory to be written to a managed unit of a separatememory device; determining, based on respective memory addresses,whether an additional portion of data associated with the managed unitis stored in the cache memory; generating a bit mask identifying a firstlocation and a second location in the managed unit, wherein the firstlocation is associated with the portion of data and the second locationis associated with the additional portion of data; and performing, basedon the bit mask, a read-modify-write operation to write the portion ofdata to the first location in the managed unit of the separate memorydevice and the additional portion of data to the second location in themanaged unit of the separate memory device.
 2. The method of claim 1,wherein performing the read-modify-write operation comprises updating aparity codeword associated with the managed unit based on the portion ofdata and the additional portion of data.
 3. The method of claim 2,wherein updating the parity codeword comprises: reading the paritycodeword from the separate memory device; performing an operation toobtain a new parity codeword based on the parity codeword and each ofthe portion of data and the additional portion of data; and writing thenew parity codeword to the managed unit to replace the parity codeword.4. The method of claim 1, wherein the first location and the secondlocation in the managed unit corresponding to the portion of data andthe additional portion of data are non-contiguous locations.
 5. Themethod of claim 1, wherein the managed unit comprises a plurality ofcodewords.
 6. The method of claim 5, wherein the portion of data iswritten to a first codeword of the plurality of codewords and theadditional portion of data is written to a second codeword of theplurality of codewords.
 7. The method of claim 1, wherein determiningwhether the additional portion of data associated with the managed unitis stored in the cache memory comprises: determining a base address ofthe managed unit; identifying an address of the additional portion ofdata; and determining whether the address of the additional portion ofdata is located within a defined address range from the base address ofthe managed unit.
 8. A system comprising: a cache memory; a separatememory device; and a processing device, operatively coupled with thecache memory and the separate memory device, to perform operationscomprising: identifying a portion of data in the cache memory to bewritten to a managed unit of the separate memory device; determining,based on respective memory addresses, whether an additional portion ofdata associated with the managed unit is stored in the cache memory;generating a bit mask identifying a first location and a second locationin the managed unit, wherein the first location is associated with theportion of data and the second location is associated with theadditional portion of data; and performing, based on the bit mask, aread-modify-write operation to write the portion of data to the firstlocation in the managed unit of the separate memory device and theadditional portion of data to the second location in the managed unit ofthe separate memory device.
 9. The system of claim 8, wherein performingthe read-modify-write operation comprises updating a parity codewordassociated with the managed unit based on the portion of data and theadditional portion of data.
 10. The system of claim 9, wherein updatingthe parity codeword comprises: reading the parity codeword from theseparate memory device; performing an operation to obtain a new paritycodeword based on the parity codeword and each of the portion of dataand the additional portion of data; and writing the new parity codewordto the managed unit to replace the parity codeword.
 11. The system ofclaim 8, wherein the first location and the second location in themanaged unit corresponding to the portion of data and the additionalportion of data are non-contiguous locations.
 12. The system of claim 8,wherein the managed unit comprises a plurality of codewords.
 13. Thesystem of claim 12, wherein the portion of data is written to a firstcodeword of the plurality of codewords and the additional portion ofdata is written to a second codeword of the plurality of codewords. 14.The system of claim 8, wherein determining whether the additionalportion of data associated with the managed unit is stored in the cachememory comprises: determining a base address of the managed unit;identifying an address of the additional portion of data; anddetermining whether the address of the additional portion of data islocated within a defined address range from the base address of themanaged unit.
 15. A non-transitory computer-readable storage mediumcomprising instructions that, when executed by a processing device,cause the processing device to execute operations comprising:identifying a portion of data in a cache memory to be written to amanaged unit of a separate memory device; determining, based onrespective memory addresses, whether an additional portion of dataassociated with the managed unit is stored in the cache memory;generating a bit mask identifying a first location and a second locationin the managed unit, wherein the first location is associated with theportion of data and the second location is associated with theadditional portion of data; and performing, based on the bit mask, aread-modify-write operation to write the portion of data to the firstlocation in the managed unit of the separate memory device and theadditional portion of data to the second location in the managed unit ofthe separate memory device.
 16. The non-transitory computer-readablestorage medium of claim 15, wherein performing the read-modify-writeoperation comprises updating a parity codeword associated with themanaged unit based on the portion of data and the additional portion ofdata.
 17. The non-transitory computer-readable storage medium of claim16, wherein updating the parity codeword comprises: reading the paritycodeword from the separate memory device; performing an operation toobtain a new parity codeword based on the parity codeword and each ofthe portion of data and the additional portion of data; and writing thenew parity codeword to the managed unit to replace the parity codeword.18. The non-transitory computer-readable storage medium of claim 15,wherein the first location and the second location in the managed unitcorresponding to the portion of data and the additional portion of dataare non-contiguous locations.
 19. The non-transitory computer-readablestorage medium of claim 15, wherein the managed unit comprises aplurality of codewords, and wherein the portion of data is written to afirst codeword of the plurality of codewords and the additional portionof data is written to a second codeword of the plurality of codewords.20. The non-transitory computer-readable storage medium of claim 15,wherein determining whether the additional portion of data associatedwith the managed unit is stored in the cache memory comprises:determining a base address of the managed unit; identifying an addressof the additional portion of data; and determining whether the addressof the additional portion of data is located within a defined addressrange from the base address of the managed unit.